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128K x 24 Three Megabit 3.3V CMOS Static RAM
IDT7MMV4101
x x
Features
High density 3 megabit 3.3V static RAM Low profile 119 lead, 14mm x 22mm BGA (Ball Grid Array) Fast RAM access times: 10,12,15ns Single 3.3V power supply Multiple Vcc & GND pins for maximum noise immunity Inputs/outputs directly LVTTL compatible Commercial (0O C to +70O C) Industrial (-40O C to +85O C) temperature options - Commercial: 10 / 12 / 15 ns - Industrial: 12 / 15 ns
Description
The IDT7MMV4101 is a three megabit static RAM constructed on an multilayer laminate substrate using three 3.3V, 128K x 8 (IDT71V124) static RAMS encapsulated in a Ball Grid Array (BGA). The IDT7MMV4101 is packaged in a plastic BGA. The BGA configuration allows 119 leads to be placed on a package 14mm by 22mm. At a maximum of 3.5mm high, this low-profile surface mount package is ideal for ultra dense systems. All inputs and outputs of the IDT7MMV4101 are LVTTL compatible and operate from a single 3.3V supply. Full asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
x x x x x
Pin Names
I/O0 - 23 A0 - 16 CS WE OE VCC GND NC Data Inputs/Outputs Addresses Chip Select Write Enable Output Enable Power Ground No Connect
4083 tbl 01
Functional Block Diagram
A0-16 CS WE OE
17
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
8
8
8
,
I/O0-7
I/O8-15
I/O16-23
4083 drw 01
Pin Configuration
7
NC
NC A8 A7 CS A6 A5
I/O0 NC NC NC NC NC
I/O1 VCC
I/O2 I/O3
I/O4 I/O5 NC
I/O6 I/O7 I/O8 I/O9 I/O10
I/O11 NC NC NC NC NC NC
NC
6 A4 5 A3 4 A2 3 A1 2 A0
GND VCC GND VCC GND VCC GND VCC GND VCC
A12 A16 A11 A15 WE OE A10 A14 A9 A13
GND VCC GND VCC GND VCC GND VCC GND VCC GND GND GND GND GND GND GND GND GND GND GND GND
GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC GND VCC
,
1 NC NC A B
I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC C D E F G H J K L M N P R T U
4083 drw 02
Top View
1
(c)2003 Integrated Device Technology, Inc.
JANUARY 2003
DSC-4083/05
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
Capacitance (TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter
(1)
Truth Table
Unit pF pF
4083 tbl 02
Conditions VIN = 3dV VOUT = 3dV
Max. 20 10
Mode Standby Read Write Outputs Disabled
CS H L L L
OE X L X H
WE X H L H
I/O High-Z DATAOUT DATAIN High-Z
Power Standby Active Active Active
4083 tbl 04
Input Capacitance I/O Capacitance
NOTE: 1. This parameter is guaranteed by design but not tested.
Recommended DC Operating Conditions
Symbol VCC(1) VCC(2) GND VIH VIL Parameter Supply Voltage Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.15 3.0 0 2.0 -0.3(3) Typ. 3.3 3.3 0
____
Absolute Maximum Ratings(1)
Symbol VCC Unit V V V V V
4083 tbl 03
Rating Supply Voltage Relative to GND
Commercial -0.5 to +4.6
Industrial -0.5 to +4.6
Unit V V C C C mA
4083 tbl 05
Max. 3.6 3.6 0 VCC + 0.3(4) 0.8
VTERM TA TBIAS TSTG IOUT
Terminal Voltage with -0.5 to VCC+0.5 -0.5 to VCC+0.5 Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current 0 to +70 -10 to +85 -55 to +125 50 -40 to +85 -10 to +85 -55 to +125 50
____
NOTES: 1. For 7MMV4101S10BG only. 2. For all speed grades except 7MMV4101S10BG. 3. VIL (min) = -1.5V for pulse width less than 5ns, once per cycle. 4. VIH (max) = Vcc + 1.5V for pulse width less than 5ns, once per cycle.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (VCC = 3.3V 10%)
Symbol IILII IILOI VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS > VIH, VOUT = GND to VCC, IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
____
Max. 15 5 0.4
____
Unit A A V V
4083 tbl 06
____
____
2.4
-10(1) Symbol ICC ISB ISB1 Parameter Dynamic Operating Current Standby Power Supply Current Full Standby Power Supply Current Test Condition VCC = Max., CS < VIL, f = fMAX, Outputs Open VCC = Max., CS > VIH, f = fMAX, Outputs Open CS > VCC - 0.2V, f =0 VIN > VCC - 0.2V or < 0.2V Max. 295 95 10
-12 Max. 275 85 10
-15 Max. 255 85 10 Unit mA mA mA
4083 tbl 07
NOTES: 1. Commercial temperature only, Vcc = -5% to +10%.
2
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
4083 tbl 08
+3.3 V
+3.3 V
298 DATA OUT
298 DATA OUT
216
30 pF
216
5 pF*
,
4083 drw 03
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ, tOHZ, tCHZ, tCLZ, tWHZ, tOW)
* Includes scope and jig.
6.42 3
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (2)
(VCC = 3.3V 10%)
-10(3) Symbol Parameter Min. Max. Min. -12 Max. Min. -15 Max. Unit
Read Cycle
tRC tAA tACS tCLZ(1) tOE tOLZ(1) tCHZ(1) tOHZ(1) tOH tPU(1) tPD(1) Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z Chip Deselect to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time 10
____ ____ ____
12
____ ____
____
15
____ ____
____
ns ns ns ns ns ns ns ns ns ns ns
10 10
____
12 12
____
15 15
____
3
____
3
____
3
____
4
____
6
____
7
____
0
____
0
____
0
____
5 5
____
6 6
____
7 7
____
____
____
____
3 0
____
3 0
____
3 0
____
____
____
____
10
12
15
Write Cycle
tWC tCW tAW tAS tWP tWR tWHZ(1) tDW tDH tOW
(1)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Write Enable to Output in High-Z Data to Write Time Overlap Data Hold from Write Time Output Active from End-of-Write
10 8 8 0 8 0
____
____
12 10 10 0 10 0
____
____
15 12 12 0 12 0
____
____
ns ns ns ns ns ns ns ns ns ns
4083 tbl 09
____
____
____
____ ____
____ ____
____ ____
____
____
____
____
____
____
5
____
5
____
5
____
6 0 3
6 0 3
7 0 3
____
____
____
____
____
____
NOTES: 1. This parameter is guaranteed by design but not tested. 2. These specifications are for the individual 71V124 Static RAMs. 3. Commercial temperature only, VCC = -5% to +10%.
4
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE CS tOLZ
(5)
tACS(3) tCLZ DATAOUT
(5)
tOHZ (5) tCHZ (5) DATAOUT VALID
4083 drw 04
, .
HIGH IMPEDANCE
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
4083 drw 05
.
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
6.42 5
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,4,5)
tWC ADDRESS tAW CS tAS WE tWHZ DATAOUT
(4) (5)
tWP
(3)
tWR
tOW HIGH IMPEDANCE
(5)
tCHZ
(4)
(5)
tDW DATAIN DATAIN VALID
tDH
4083 drw 06
.
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC ADDRESS tAW CS tAS WE tDW DATAIN DATAIN VALID
4083 drw 07
tCW
tWR
(3)
tDH
.
NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured 200mV from steady state.
6
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
Package Dimensions
22.0 + 0.1
QP ON ML K
20.32 Ref
J I H G F E D C BA
7 6 5
14.00 + 0.1 3.19 REF
4 3 2 1
7.62 Ref
,
1.27 Typ TOP VIEW 0.84 REF BOTTOM VIEW
2.15 Nom. 2.36 Max
4083 drw 08
NOTES: 1. All dimensions are in mm.
Ordering Information
IDT XXXXX Device Type X Power X Speed X Package X Process/ Temperature Range
I Blank BG 10 12 15 S Industrial (-40C to +85C) Commercial (0C to +70C) 119 lead BGA (Ball Grid Array) Speed in Nanoseconds Commercial Temp Only Commercial and Industrial Temp Commercial and Industrial Temp Standard Power
,
7MMV4101 3 Megabit Static RAM
4083 drw 09
6.42 7
IDT7MMV4101 128K x 24 Three Megabit 3.3V CMOS Static RAM
Commercial and Industrial Temperature Ranges
Datasheet History
09/18/00 Pg. 2 01/07/03 Add datasheet history Reduce ICC, ISB, and ISB1 to reflect K step die shrink Changed datasheet from Prelininary to final release
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax:408-492-8674 www.idt.com
8
for Tech Support: sramhelp@idt.com 800 544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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